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| 12-Bit, 80 MSPS, 3 V A/D Converter AD9236 FEATURES Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70.4 dBc to Nyquist SFDR = 87.8 dBc to Nyquist Low power: 366 mW Differential input with 500 MHz bandwidth On-chip reference and sample-and-hold DNL = 0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD AD9236 VIN+ SHA VIN- 4 REFT REFB CORRECTION LOGIC 12 OUTPUT BUFFERS D11 (MSB) VREF OTR A/D MDAC1 8-STAGE 1 1/2-BIT PIPELINE 16 A/D 3 APPLICATIONS High end medical imaging equipment IF sampling in communications receivers WCDMA, CDMA-One, CDMA-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes DTV subsystems SENSE REF SELECT 0.5V CLOCK DUTY CYCLE STABILIZER MODE SELECT D0 (LSB) AGND CLK PDWN MODE DGND 03066-0-001 Figure 1. GENERAL DESCRIPTION The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS analog-to-digital converter featuring a high performance sampleand-hold amplifier (SHA) and voltage reference. The AD9236 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and common modes, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9236 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP and is specified over the industrial temperature range (-40C to +85C). PRODUCT HIGHLIGHTS 1. The AD9236 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz, and can be configured for single-ended or differential operation. 4. The AD9236 is pin compatible with the AD9215, AD9235, and AD9245. This allows a simplified migration from 10 bits to 14 bits and 20 MSPS to 80 MSPS. 5. The DCS maintains overall ADC performance over a wide range of clock pulse widths. 6. The OTR output bit indicates when the signal is beyond the selected input range. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved. AD9236 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 5 Switching Specifications .................................................................. 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Terminology ...................................................................................... 8 Pin Configurations and Function Descriptions ........................... 9 Equivalent Circuits......................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 14 Analog Input and Reference Overview ................................... 14 Clock Input Considerations...................................................... 15 Power Dissipation and Standby Mode .................................... 16 Digital Outputs ........................................................................... 16 Timing ......................................................................................... 17 Voltage Reference ....................................................................... 17 Operational Mode Selection ..................................................... 18 Evaluation Board ........................................................................ 18 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 34 REVISION HISTORY 1/06--Rev. A to Rev. B Changes to Figure 29...................................................................... 15 Changes to Equation in Jitter Considerations Section .............. 16 Changes to Internal Reference Connection Section, Figure 34, and Table 10..................................................................................... 17 Changes to Figure 35...................................................................... 18 Changes to Figure 38...................................................................... 20 Changes to Figure 39...................................................................... 21 Changes to Figure 48...................................................................... 27 Changes to Figure 49...................................................................... 28 Changes to Figure 50...................................................................... 29 Changes to Table 12........................................................................ 32 Updated Outline Dimensions ....................................................... 33 Changes to Ordering Guide .......................................................... 34 10/03--Rev. 0 to Rev. A Changes to Figure 30...................................................................... 15 Changes to Figure 33 ..................................................................... 17 Changes to Figure 40...................................................................... 22 Changes to Figure 49...................................................................... 28 Changes to Figure 50...................................................................... 29 Changes to Table 11 ....................................................................... 32 Changes to Ordering Guide ......................................................... 33 Rev. B | Page 2 of 36 AD9236 DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error 1 Gain Error Gain Error1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error1 Gain Error Gain Error1 INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance 3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD 4 IDRVDD4 PSRR POWER CONSUMPTION Low Frequency Input4 Standby Power 5 1 2 Temp Full Full Full 25C Full Full Full Full Full Full Full 25C 25C 25C 25C 25C Full Full Full Full Test Level VI VI VI V VI VI VI V V V VI V V V V V IV IV V V Min 12 AD9236BRU/AD9236BCP Typ Max Unit Bits Guaranteed 0.30 0.10 0.30 0.40 0.35 6 12 18 2 0.8 1 0.1 0.55 0.28 1 2 7 7 1.30 4.34 0.65 1.20 % FSR % FSR % FSR LSB LSB ppm/C ppm/C ppm/C 35 mV mV mV mV LSB rms LSB rms V p-p V p-p pF k Full Full Full 25C 25C 25C 25C IV IV VI V V V V 2.7 2.25 3.0 2.5 122 8 0.01 366 1.0 3.6 3.6 137 V V mA mA % FSR mW mW With a 1.0 V internal reference. Measured at low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Measured at AC Specifications conditions without output drivers. 5 Measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND). Rev. B | Page 3 of 36 AD9236 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = -0.5 dBFS, DCS off, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz WORST SECOND OR THIRD fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz Temp Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Full 25C 25C Test Level VI V V IV V V VI V V IV V V VI V V IV V V VI V V VI V V VI V V IV V V 75.6 91.3 87.8 73.2 81.4 76.4 Min 68.6 70.9 70.4 67.8 70.1 69.0 68.4 70.8 70.2 67.4 69.8 68.0 11.1 11.5 11.4 10.9 11.3 11.0 -75.6 -91.3 -87.8 -73.2 -81.4 -76.4 AD9236BRU/AD9236BCP Typ Max Unit dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Rev. B | Page 4 of 36 AD9236 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, 1.0 V external reference, unless otherwise noted. Table 3. Parameter LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUTS (D0-D11, OTR) 1 DRVDD = 3.3 V High Level Output Voltage (IOH = 50 A) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 A) DRVDD = 2.5 V High Level Output Voltage (IOH = 50 A) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 A) 1 Temp Full Full Full Full Full Test Level IV IV IV IV V AD9236BRU/AD9236BCP Min Typ Max 2.0 -10 -10 2 0.8 +10 +10 Unit V V A A pF Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 3.29 3.25 0.2 0.05 2.49 2.45 0.2 0.05 V V V V V V V V Output voltage levels measured with 5 pF load on each output. Rev. B | Page 5 of 36 AD9236 SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse Width High 1 CLK Pulse Width Low1 DATA OUTPUT PARAMETERS Output Propagation Delay (tPD) 2 Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 3 OUT OF RANGE RECOVERY TIME 1 2 3 Temp Full Full Full Full Full Full Full Full Full Full Full Test Level VI V V V V V V V V V V Min 80 AD9236BRU/AD9236BCP Typ Max Unit MSPS MSPS ns ns ns ns Cycles ns ps rms ms Cycles 1 12.5 4.0 4.0 3.5 7 1.0 0.3 7 2 With duty cycle stabilizer (DCS) enabled. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB. N N-1 ANALOG INPUT N+1 N+2 N+8 N+3 N+4 N+5 N+6 N+7 tA CLK DATA OUT N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 2.0ns MIN N-1 N tPD = 6.0ns MAX 03066-0-002 Figure 2. Timing Diagram Table 5. Explanation of Test Levels Test Level I II III IV V VI Definitions 100% production tested. 100% production tested at 25C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C and guaranteed by design and characterization for industrial temperature range. Rev. B | Page 6 of 36 AD9236 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD D0 to D11 DGND CLK, MODE AGND VIN+, VIN- AGND VREF AGND SENSE AGND REFT, REFB AGND PDWN AGND ENVIRONMENTAL Storage Temperature Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature With Respect to Min -0.3 -0.3 -0.3 -3.9 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65 -40 Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +125 +85 300 150 Unit V V V V V V V V V V V C C C C THERMAL RESISTANCE JA is specified for the worst-case conditions on a 4-layer board in still air, in accordance with EIA/JESD51-1. Table 7. Package Type RU-28 CP-32-2 JA 67.7 32.5 JC 32.71 Unit C/W C/W Airflow increases heat dissipation effectively, reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 36 AD9236 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 11/2 LSB below positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD) 1 The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Signal-to-Noise and Distortion (SINAD)1 The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula ENOB = (SINAD - 1.76 ) 6.02 Signal-to-Noise Ratio (SNR)1 The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious Free Dynamic Range (SFDR)1 The difference in dB between the rms input signal amplitude and the peak spurious signal. The peak spurious component may or may not be a harmonic. Two-Tone SFDR1 The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. B | Page 8 of 36 AD9236 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 31 AGND 28 AGND 32 AVDD 27 AVDD 25 REFB 26 REFT OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ 1 2 3 4 5 6 7 8 9 28 D11 (MSB) 27 D10 26 D9 25 D8 24 DRVDD DNC 1 CLK 2 DNC 3 PDWN 4 DNC 5 DNC 6 (LSB) D0 7 D1 8 29 VIN+ 30 VIN- 24 VREF 23 SENSE 22 MODE 21 OTR 20 D11 (MSB) 19 D10 18 D9 17 D8 DGND 15 DRVDD 16 D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 AD9236 TOP VIEW (Not to Scale) 23 DGND 22 D7 21 D6 20 D5 19 D4 18 D3 17 D2 16 D1 15 D0 (LSB) AD9236 CSP TOP VIEW (Not to Scale) VIN- 10 AGND 11 AVDD 12 CLK 13 PDWN 14 03066-0-021 03066-0-022 Figure 3. 28-Lead TSSOP Figure 4. 32-Lead LFCSP Table 8. Pin Function Descriptions--28-Lead TSSOP Pin No. 1 2 3 4 5 6 7, 12 8, 11 9 10 13 14 15 to 22, 25 to 28 23 24 Mnemonic OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- CLK PDWN D0 (LSB) to D11 (MSB) DGND DRVDD Description Out-of-Range Indicator Data Format Select and DCS Mode Selection Reference Mode Selection Voltage Reference Input/Output Differential Reference (-) Differential Reference (+) Analog Power Supply Analog Ground Analog Input Pin (+) Analog Input Pin (-) Clock Input Pin Power-Down Function Select Data Output Bits Digital Output Ground Digital Output Driver Supply Table 9. Pin Function Descriptions--32-Lead LFCSP Pin No. 1, 3, 5, 6 2 4 7 to 14, 17 to 20 15 16 21 22 23 24 25 26 27, 32 28, 31 29 30 Mnemonic DNC CLK PDWN D0 (LSB) to D11 (MSB) DGND DRVDD OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- Description Do Not Connect Clock Input Pin Power-Down Function Select Data Output Bits Digital Output Ground Digital Output Driver Supply Out-of-Range Indicator Data Format Select and DCS Mode Selection Reference Mode Selection Voltage Reference Input/Output Differential Reference (-) Differential Reference (+) Analog Power Supply Analog Ground Analog Input Pin (+) Analog Input Pin (-) Rev. B | Page 9 of 36 AD9236 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN- D11-D0, OTR 03600-0-003 03600-0-005 Figure 5. Equivalent Analog Input Circuit AVDD Figure 7. Equivalent Digital Output Circuit AVDD MODE 20k CLK, PDWN 03600-0-004 03600-0-006 Figure 6. Equivalent MODE Input Circuit Figure 8. Equivalent Digital Input Circuit Rev. B | Page 10 of 36 AD9236 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V, sample rate = 80 MSPS, DCS disabled, TA = 25C, 2 V p-p differential input, AIN = -0.5 dBFS, VREF = 1.0 V external, unless otherwise noted. 0 -10 -20 -30 AIN = -0.5dBFS SNR = 71.0dBc ENOB = 11.5 BITS SFDR = 93.6dBc 100 SFDR (dBFS) 90 SNR/SFDR (dBc AND dBFS) SFDR (dBc) 80 SFDR = 90dB REFERENCE LINE 70 SNR (dBFS) 60 SNR (dBc) 50 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 03066-0-031 40 -30 -25 -20 -15 -10 -5 0 03066-0-048 INPUT AMPLITUDE (dBFS) Figure 9. Single Tone 8K FFT @ 2.5 MHz Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz 0 -10 -20 -30 AIN = -0.5dBFS SNR = 70.6dBc ENOB = 11.4 BITS SFDR = 87.8dBc 100 SFDR (dBFS) 90 SNR/SFDR (dBc AND dBFS) SFDR (dBc) 80 SFDR = 90dB REFERENCE LINE 70 SNR (dBFS) 60 SNR (dBc) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 03066-0-032 50 40 -30 -25 -20 -15 -10 -5 0 03066-0-049 INPUT AMPLITUDE (dBFS) Figure 10. Single Tone 8K FFT @ 39 MHz Figure 13. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz 0 -10 -20 -30 AIN = -0.5dBFS SNR = 70.1dBc ENOB = 11.3 BITS SFDR = 81.9dBc 100 SFDR (DIFF) 90 AMPLITUDE (dBFS) SNR/SFDR (dBc) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 03066-0-033 SFDR (SE) 80 SNR (DIFF) 70 SNR (SE) 60 50 0 20 40 60 80 100 03066-0-042 SAMPLE RATE (MSPS) Figure 11. Single Tone 8K FFT @ 70 MHz Figure 14. SNR/SFDR vs. Sample Rate @ 10 MHz Rev. B | Page 11 of 36 AD9236 0 -10 -20 -30 SNR/SFDR (dBc AND dBFS) 90 SFDR (dBc) 80 AIN = -6.5dBFS SNR = 71.3dBFS SFDR = 92.5dBc SFDR (dBFS) 100 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 03066-0-036 70 SNR (dBFS) 60 SFDR = 90dB REFERENCE LINE SNR (dBc) 50 40 -30 -27 -24 -21 -18 -15 -12 -9 -6 INPUT AMPLITUDE (dBFS) 03066-0-039 Figure 15. Two-Tone 8K FFT @ 30 MHz and 31 MHz Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz 0 -10 -20 -30 SNR/SFDR (dBc AND dBFS) 100 AIN = -6.5dBFS SNR = 71.0dBFS SFDR = 79.3dBc 90 SFDR (dBc) 80 SFDR (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 03066-0-037 70 SNR (dBFS) 60 SFDR = 90dB REFERENCE LINE 50 SNR(dBc) 40 -30 -27 -24 -21 -18 -15 -12 -9 -6 INPUT AMPLITUDE (dBFS) 03066-0-040 Figure 16. Two-Tone 8K FFT @ 69 MHz and 70 MHz Figure 19. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 03066-0-038 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 3072 4096 0 1024 2048 CODE 3072 4096 03066-0-041 Figure 17. Typical INL Figure 20. Typical DNL Rev. B | Page 12 of 36 AD9236 72.0 71.5 95 71.0 70.5 SNR (dBc) 100 -40C 90 +25C SFDR (dBc) -40C +85C 85 +25C 80 70.0 69.5 69.0 +85C 75 68.5 68.0 0 25 50 75 100 125 03066-0-045 70 0 25 50 75 100 125 03066-0-047 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 21. SNR vs. Input Frequency Figure 24. SFDR vs. Input Frequency 95 SFDR (DCS ON) 90 0 -10 -20 85 SNR/SFDR (dBc) SFDR (DCS OFF) AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 80 SNR (DCS OFF) 75 70 65 SNR (DCS ON) 60 55 30 -100 -110 -120 35 40 45 50 55 60 65 70 0 7.68 15.36 FREQUENCY (MHz) 23.04 30.72 03066-0-061 DUTY CYCLE (%) 03066-0-046 Figure 22. SNR/SFDR vs. Clock Duty Cycle Figure 25. 32K FFT WCDMA Carrier @ FIN =76.8 MHz, Sample Rate = 61.44 MSPS 0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 7.68 15.36 FREQUENCY (MHz) 03066-0-060 23.04 30.72 Figure 23. 32K FFT CDMA-2000 Carrier @ FIN = 46.08 MHz, Sample Rate = 61.44 MSPS Rev. B | Page 13 of 36 AD9236 THEORY OF OPERATION The AD9236 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. Referring to Figure 27, the clock signal alternately switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. In addition, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC's input; therefore, the precise values are dependant upon the application. In IF undersampling applications, any shunt capacitors should be reduced or removed. In combination with the driving source impedance, they would limit the input bandwidth. H T 5pF VIN+ CPAR T T 5pF VIN- CPAR T H 03066-0-012 Figure 27. Switched-Capacitor SHA Input ANALOG INPUT AND REFERENCE OVERVIEW The analog input to the AD9236 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range (VCM) and maintain excellent performance, as shown in Figure 26. An input common-mode voltage of midsupply minimizes signaldependant errors and provides optimum performance. 100 95 SFDR (2.5MHz) 90 85 SNR/SFDR (dBc) For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as follows: REFT = 1/2(AVDD + VREF) REFB = 1/2(AVDD + VREF) Span = 2 x (REFT - REFB) = 2 x VREF 80 75 SFDR (39MHz) SNR (2.5MHz) 70 SNR (39MHz) 65 60 55 50 0.5 1.0 1.5 2.0 2.5 3.0 03066-0-016 It can be seen from the previous equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The internal voltage reference can be pin strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9236 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. COMMON-MODE LEVEL (V) Figure 26. SNR, SFDR vs. Common-Mode Level Rev. B | Page 14 of 36 AD9236 The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: 33 2V p-p 49.9 20pF 33 AVDD VIN+ AD9236 VIN- AGND VCM MIN = VCM MAX = VREF 2 ( AVDD + VREF ) 2 0.1F 1k 1k 03600-0-014 The minimum common-mode input level allows the AD9236 to accommodate ground referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source can be applied to VIN+ or VIN-. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal can be applied to VIN+ while a 1 V reference is applied to VIN-. The AD9236 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance can degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies. Figure 29. Differential Transformer-Coupled Configuration The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing (see Figure 14). However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 30 details a typical single-ended input configuration. Differential Input Configurations As previously detailed, optimum performance is achieved while driving the AD9236 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 1k 2V p-p 49.9 0.33F 1k 1k + 10F 0.1F 1k 33 20pF 33 AVDD VIN+ AD9236 VIN- AGND 03600-A-015 1V p-p 49.9 499 1k 523 499 33 20pF 33 499 Figure 30. Single-Ended Input Configuration AVDD VIN+ CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result can be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9236 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9236. As shown in Figure 22, noise and distortion performance is nearly flat for a 30% to 70% duty cycle with the DCS on. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. AD8138 AD9236 VIN- AGND 0.1F 1k 03066-0-013 Figure 28. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9236. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependent on the input frequency and source impedance and should be reduced or removed. An example is shown in Figure 29. Rev. B | Page 15 of 36 AD9236 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated with the following equation: 1 SNR = 20 log 10 2f INPUT x t J which is determined by the sample rate and the characteristics of the analog input signal. 425 ANALOG CURRENT 120 400 100 375 80 60 40 325 20 DIGITAL CURRENT 300 10 20 30 40 50 60 70 80 90 0 100 140 TOTAL POWER In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter (see Figure 31). The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9236. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 75 70 0.2ps 65 MEASURED SNR 0.5ps 350 SAMPLE RATE (MSPS) 03066-0-044 Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 32 was taken with the same operating conditions as the Typical Performance Characteristics, and with a 5 pF load on each output driver. By asserting the PDWN pin high, the AD9236 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9236 to its normal operational mode. Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 10 F decoupling capacitors on REFT and REFB, it takes approximately 1 second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation. SNR (dBc) 60 55 50 45 40 1 10 100 1.0ps 1.5ps 2.0ps 2.5ps 3.0ps 1000 03066-0-043 INPUT FREQUENCY (MHz) Figure 31. SNR vs. Input Frequency and Jitter POWER DISSIPATION AND STANDBY MODE As shown in Figure 32, the power dissipated by the AD9236 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD x CLOAD x fCLK x N I DRVDD = VDRVDD x C LOAD x f CLK x N where N is the number of output bits, 12 in the case of the AD9236. This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, DIGITAL OUTPUTS The AD9236 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies, which can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts can require external buffers or latches. As detailed in Table 11, the data format can be selected for either offset binary or twos complement. Rev. B | Page 16 of 36 CURRENT (mA) POWER (mW) AD9236 TIMING The AD9236 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9236. These transients can degrade the converter's dynamic performance. The lowest typical conversion rate of the AD9236 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance can degrade. In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 10F + 0.1F SELECT LOGIC SENSE 0.5V 0.1F + 10F VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9236. The input range can be adjusted by varying the reference voltage applied to the AD9236 using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in Table 10 and described in the following sections. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). AD9236 03066-A-017 Figure 33. Internal Reference Configuration VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF + 10F 0.1F R2 SENSE SELECT LOGIC 0.1F + Internal Reference Connection A comparator within the AD9236 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 33), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 34, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as follows: 10F R1 0.5V AD9236 03066-0-018 R2 VREF = 0.5 x 1 + R1 Figure 34. Programmable Reference Configuration Table 10. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 R2 (See Figure 34) 0 .5 x 1 + R1 Resulting Differential Span (V p-p) 2 x External Reference 1.0 2 x VREF 2.0 1.0 Rev. B | Page 17 of 36 AD9236 If the internal reference of the AD9236 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 35 depicts how the internal reference voltage is affected by loading. A 2 mA load is the maximum recommended load. 0.05 OPERATIONAL MODE SELECTION As discussed in the Digital Outputs section, the AD9236 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock duty cycle stabilizer (DCS). The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 11. Table 11. Mode Selection Duty Cycle Stabilizer Disabled Enabled Enabled Disabled 0 -0.05 ERROR (%) 0.5V ERROR (%) -0.10 1.0V ERROR (%) -0.15 MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Data Format Twos Complement Twos Complement Offset Binary Offset Binary -0.20 -0.25 0 0.5 1.0 1.5 LOAD (mA) 2.0 2.5 3.0 03066-0-019 EVALUATION BOARD The AD9236 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. It is critical that signal sources with very low phase noise (< 1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. Figure 35. VREF Accuracy vs. Load External Reference Operation The use of an external reference can be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) can be necessary to reduce gain matching errors to an acceptable level. Figure 36 shows the typical drift characteristics of the internal reference in both 1.0 V and 0.5 V modes. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1.0 V. 1.0 0.9 0.8 0.7 VREF ERROR (%) TSSOP Evaluation Board Figure 37 shows the typical bench setup used to evaluate the ac performance of the AD9236. The AD9236 can be driven singleended or differentially through an AD8138 driver or a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance (that is, IF undersampling characterization). It allows the user to apply a clock input signal that is 4x the target sample rate of the AD9236. A low jitter, differential divide-by-4 counter, the MC100LVEL33D, provides a 1x clock output that is subsequently returned back to the CLK input via JP9. For example, a 260 MHz signal (sinusoid) is divided down to a 65 MHz signal for clocking the ADC. Note that R1 must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4x that of a 1x signal of equal amplitude. 0.6 0.5 0.4 VREF = 0.5V 0.3 0.2 0.1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 VREF = 1.0V TEMPERATURE (C) 03066-0-011 Figure 36. Typical VREF Drift Rev. B | Page 18 of 36 AD9236 LFCSP Evaluation Board The typical bench setup used to evaluate the ac performance of the AD9236 is similar to the TSSOP evaluation board connections. The AD9236 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 48). An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9236 allows the user to optimize the frequency response of the op amp for their application. 3V - + - 3V + - 3V + - 3V + REFIN HP8644, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER AVDD GND DUT GND DUT S4 AVDD DRVDD XFMR INPUT AD9236 EVALUATION BOARD S1 CLOCK DVDD DATA CAPTURE AND PROCESSING J1 10MHz HP8644, 2V p-p REFOUT CLOCK SYNTHESIZER CLOCK DIVIDER 03066-0-024 Figure 37. TSSOP Evaluation Board Connections Rev. B | Page 19 of 36 AD9236 D0O D8O D9O D10O D10 D11 D11O 4 RP5 22 5 3 RP5 22 6 2 RP5 22 7 D9 D8 1 RP3 22 8 D0 22 1 RP5 8 D1O 2 RP3 22 7 D1 D2O 3 RP3 22 6 D2 D3O 4 RP3 22 5 D3 1 RP6 22 8 2 RP6 22 7 WHT TP5 JP23 JP22 DUTAVDD OTR R3 10k JP25 JP24 C22 10F 10V 0.001F C39 C36 0.1F JP12 DUTAVDD C57 0.1F 3 RP6 22 6 OTRO 4 RP6 22 5 D4O 1 RP4 22 8 D4 2 RP4 22 7 D5O D5 D6O 3 RP4 22 6 D6 4 RP4 22 5 D7O D7 TP2 L1 RED DUTAVDDIN TB1 2 FBEAD 21 C58 22F C59 0.1F F 0.1F C35 WHT TP17 R4 10k C21 10F 10V 25V AGND TP1 RED AVDD JP13 AVDD C52 0.1F 5k R27 TP3 RED JP11 DUTDRVDD JP6 JP1 JP2 C53 0.1F 1k R42 DUTAVDD C23 10F 10V C41 0.001F C38 0.1F 1k R17 JP7 C32 0.1F AVDD C33 0.1F TB1 3 AD9236 AVDDIN TB1 1 FBEAD 2 L2 1 Figure 38. TSSOP Evaluation Board Schematic, DUT Rev. B | Page 20 of 36 1k R20 C34 0.1F 10V 10F C20 L3 1 C50 0.1F L4 TP4 RED DVDD TP9 TP10 TP15 TP16 BLK BLK BLK BLK TP11 TP12 TP13 TP14 BLK BLK BLK BLK C14 0.1F C47 22F 25V VIN+ VIN- DRVDDIN TB1 5 FBEAD 2 C48 22F AVDD OTR 71 AGND D11 8 28 SENSE D10 3 27 VREF D9 4 26 PDWN D8 14 25 REFB D7 22 5 REFT D6 21 6 MODE U1 D5 2 20 VIN+ D4 19 9 VIN- D3 10 18 AGND D2 17 11 D1 AVDD 16 12 D0 DGND 15 23 DRVDD CLK 24 13 OTRO D0O D1O D2O D3O D4O D5O D6O D7O D8O D9O D10O D11O DUTCLK WHT TP6 DUTDRVDD C1 10F 10V 25V AGND TB1 4 DVDDIN TB1 6 FBEAD 21 C37 0.1F C40 0.001F C6 22F 25V 03066-0-007 R25 10k AVDD T1-1T 6 1N5712 1N5712 S5 C12 0.1F 1 2 T2 1 19 G1 G2 1 2 3 4 5 6 7 8 1 RP1 RP1 RP1 RP1 RP1 RP1 RP2 2 3 4 5 6 7 RP2 RP2 RP2 RP2 RP2 RP2 RP1 22 22 22 RP1 22 16 15 14 13 22 12 22 11 22 10 22 22 22 22 9 16 15 14 22 13 22 12 22 11 22 10 DVDD AUXCLK 1 2 5 4 VCC 20 10 18 17 16 3 R11 49.9 D2 D1 10V 2 C4 10F 1 2 4 6 8 1 3 5 7 9 11 10 12 AVDD AVDD AVDD AVDD MC100LVEL33D 8 VCC NC 7 OUT U3 INA 6 REF INB 5 VEE INCOM 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 15 14 13 12 11 C11 0.1F 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 R26 10k R12 113 R13 113 U3 DECOUPLING C26 0.1F 1 19 G1 G2 U7 74VHC541 VCC 20 GND 10 18 17 C5 10F 10V 2 1 C24 0.1F C27 0.1F C28 10F 10V GND U6 74VHC541 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DOTR DACLK 8 RP2 22 9 Figure 39. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering R15 90 HEADER RIGHT ANGLE MALE NO EJECTORS Rev. B | Page 21 of 36 D8 R2 10k CW AVDD;14 AGND;7 R14 90 13 15 17 19 21 23 25 27 29 31 33 35 37 39 14 16 18 20 22 24 26 28 30 32 34 36 38 40 JP9 J1 03066-0-008 R19 500 AVDD R18 500 CLOCK S1 TP7 WHT U8 1 2 DUTCLK JP4 U8 4 74VHC04 JP3 R9 22 OTR 74VHC04 5 U8 6 R7 22 74VHC04 D9 D10 D11 C13 1 2 0.1F 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 16 15 14 13 12 11 R1 49.9 3 U8 12 74VHC04 13 U8 10 74VHC04 8 74VHC04 AVDD C3 10F 10V C10 0.1F U8 DECOUPLING 11 U8 9 AD9236 AD9236 AVDD JP5 R23 1k C7 0.1F SINGLE INPUT S3 2 JP42 JP40 C44 DNP C9 0.33F R5 49.9 R41 1k 1 AVDD AVDD R32 1k C15 10F 10V 1+ 2 JP45 R21 33 VIN+ C69 0.33F C2 VAL C44B 20pF JP46 JP41 R6 40 VAL C42 R22 33 VIN- R33 1k C8 0.1F R37 499 3 Figure 40. TSSOP Evaluation Board Schematic, Analog Inputs Rev. B | Page 22 of 36 VCC 4 VO+ -IN 2 1 VOC U2 8 +IN VO- AD8138 VEE 5 R10 40 6 VAL R36 499 VAL C17 C45 T1-1T 6 R24 49.9 5 4 T1 1 2 3 XFMR INPUT 1 S4 2 B R34 523 JP43 C43 DNP AMP INPUT 1 S2 R35 499 2 R31 49.9 C18 0.1F AVDD 10V 12 R16 1k C19 10F 1 A 2 JP8 ALT VEE TP8 RED 3 R8 1k C25 0.33F C16 0.1F 03066-A-009 AD9236 DACLK DVDD C30 0.1F C31 0.01F C29 0.1F C46 0.01F TP18 WHT C56 0.01F S6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 MSB-DB11 CLOCK DB10 DVDD DB19 DCOM DB8 AD9762 NC3 DB7 AVDD DB6 COMP2 DB5 IOUTA U4 DB4 IOUTB DB3 ACOM DB2 COMP1 DB1 FSADJ DB0 REFIO NC1 REFLO SLEEP NC2 R29 49.9 C55 22pF R28 49.9 C54 22pF C51 0.01F R30 2k C49 0.01F 03066-0-010 Figure 41. TSSOP Evaluation Board Schematic, Optional D/A Converter 03066-0-025 Figure 42. TSSOP Evaluation Board Layout, Primary Side Rev. B | Page 23 of 36 AD9236 03066-0-026 Figure 43. TSSOP Evaluation Board Layout, Secondary Side 03066-0-027 Figure 44. TSSOP Evaluation Board Layout, Ground Plane Rev. B | Page 24 of 36 AD9236 03066-0-028 Figure 45. TSSOP Evaluation Board Layout, Power Plane 03066-0-029 Figure 46. TSSOP Evaluation Board Layout, Primary Silkscreen Rev. B | Page 25 of 36 AD9236 03066-0-030 Figure 47. TSSOP Evaluation Board Layout, Secondary Silkscreen Rev. B | Page 26 of 36 GND EXTREF 1V MAX E1 AVDD P6 1 H1 MTHOLE6 H2 MTHOLE6 R1 10k AVDD C13 GND 0.10F P11 P9 P8 1 4 6 5 2 3 C22 10F P2 R5 1k H3 MTHOLE6 H4 MTHOLE6 GND GND VDL 2.5V P7 A B C D P1 GND GND p10 2 R7 1k 3.0V AVDD 2.5V DRVDD R9 10k 0.1F C12 P3 3 C8 0.1F GND R6 1k C9 0.10F 4 C29 10F 0.1F C11 GND P4 GND GND OVERRANGE BIT (MSB) 1 RP2 220 16 2 3 15 14 4 5 6 7 8 16 15 14 DRVDD GND 13 12 11 10 9 GND C7 0.1F 5.0V VAMP E MODE 2 P5 DRX D13X D12X D11X 24 23 22 21 20 19 FOR SINGLE ENDED INPUT PLACE R18, R19, R42, C6, AND C18. REMOVE R3, R12, C15, C17, AND C27. GND 18 17 D10X D9X D8X D7X C6 0.1F AVDD GND R36 1k R26 1k 25 REFB R42 0 R12, R42, C17 ONLY ONE SHOULD BE ON BOARD AT A TIME. AMPIN R12 XOUT T1 ADT1-1WT GND GND XOUTB R3 0 AMPINB C18 0.10F R SINGLE ENDED R11 36 C5 0.1F OR L1 FOR FILTER GND 1 DNC 2 CLK 3 DNC 4 PDWN 5 DNC 6 DNC 7 D0 8 D1 Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs and DUT VREF SENSE MODE OTR D11 D10 D9 D8 Rev. B | Page 27 of 36 AD9236 U4 AVDD GND VIN+ VIN- GND AVDD R4 33 C21 10pF GND GND C16 0.1F GND R2 XX C19 20pF 26 REFT 27 AVDD 28 AGND 29 VIN+ 30 VIN- 31 AGND 32 AVDD 13 12 11 10 D2 9 (LSB) 1 2 3 4 5 6 7 8 RP1 220 16 15 14 13 12 11 10 9 DRVDD DGND D7 D6 D5 D4 D3 D6X D5X D4X D3X D2X D1X D0X J1 6 2 CT 4 L1 10nH C26 10pF C15 AMP 0.1F PRI SEC XFRIN1 1 5 NC 3 GND R10 36 E 45 OPTIONAL XFR T2 FT C1-1-13 5 1 XOUT X FRIN 2 CT 3 4 GND XOUTB C23 10pF R15 33 CLK R8 1k P14 SENSE PIN SOLDERABLE JUMPER: E TO A: EXTERNAL VOLTAGE DIVIDER E TO B: INTERNAL 1V REFERENCE (DEFAULT) E TO C: EXTERNAL REFERENCE E TO D: INTERNAL 0.5V REFERENCE PRI SEC R18 25 AVDD AVDD GND R13 1k R25 1k P13 GND MODE PIN SOLDERABLE JUMPER: 5 TO 1: TWOS COMPLEMENT/DCS OFF 5 TO 2: TWOS COMPLEMENT/DCS ON 5 TO 3: OFFSET BINARY/DCS ON 5 TO 4: OFFSET BINARY/DCS OFF R3, R16, C18 ONLY ONE SHOULD BE ON BOARD AT A TIME GND 03066-A-050 AD9236 74LVTH162374 U1 25 2QB DRY GND 2 4 6 7 7 8 10 3 5 3 5 1 GND MSB GND 10 12 DRVDD DR 4 6 8 2 P12 1 24 2CLK 2OE HEADER 40 GND AD9236 CLKAT/DAC MSB DRX D13X GND D12X D11X DRVDD D10X D9X GND GND D8X D7X D6X GND D5X GND D4X D3X CC DRVDD 1Q4 GND 7 6 DRY 23 2Q7 22 GND 21 2Q6 20 2Q5 19 VCC 18 2Q4 17 2Q3 16 GND 15 2Q2 14 2Q1 13 1Q8 12 1Q7 11 GND 10 1Q6 9 1Q5 8 V DRVDD D2X D1X LSB 1 OUT R38 1k R39 1k GND VAMP C24 10F GND C44 0.1F VAMP GND GND D0X 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 36 36 38 38 40 40 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 35 35 37 37 39 39 GND GND CLKLAT/DAC IN 2DB 26 2D7 27 GND 28 2D6 29 2D5 30 V 31 CC 2D4 32 2D3 33 GND 34 2D2 35 2D1 36 1D8 37 1D7 38 GND 39 1D6 40 1D5 41 VCC 42 1D4 43 1D3 44 GND 45 1D2 46 1D1 47 1CLK 48 1Q3 5 GND 4 1Q2 3 1Q1 2 1OE 1 Figure 49. LFCSP Evaluation Board Schematic, Digital Path Rev. B | Page 28 of 36 GND GND C45 0.1F GND R41 10k R40 10k TO USE AMPLIFIER PLACE ALL COMPONENTS SHOWN HERE (RIGHT) EXCEPT R40 OR R41. REMOVE R12, R3, R18, R42, C6, C15, AND C18. POWER DOWN USE R40 OR R41 VAMP U3 AD8351 10 VOCM 9 VPOS 8 OPHI 7 OPLO 6 COMM R34 1.2k AMP IN INHI 3 INLO 4 C35 0.10F R35 25 AMP C28 0.1F PWDN 1 RGP1 2 R14 25 AMPINB R16 0 C27 0.1F R19 50 AMPIN GND R17 0 C17 0.1F 03066-A-051 R33 RPG2 5 25 GND GND VDL DRVDD DRVDD VDL C2 10F C49 0.001F C20 10F GND DIGITAL BYPASSING LATCH BYPASSING GND ANALOG BYPASSING C30 0.001F C31 0.1F C34 0.1F C36 0.1F C38 0.001F C1 C39 0.001F 0.1F C47 0.1F C48 0.001F C25 10F C32 0.001F C33 C14 0.1F 0.001F C41 0.1F AVDD AVDD C10 10F C4 10F C3 10F C37 0.1F C40 0.001F GND GND DUT BYPASSING VAMP CLOCK TIMING ADJUSTMENTS GND C46 10F FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 R28 0 ENC 74VCX86 ENCX 3 6 7 GND GND CLK ENCX ENC E50 1 1A 2 1B 4 2A 1Y 2Y 3Y 14 PWR R27 0 R32 1k R23 0 E51 SCHEMATIC SHOWS TWO GATE DELAY SETUP. FOR ONE DELAY, REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0). Figure 50. LFCSP Evaluation Board Schematic, Clock Input 2B 8 11 VDL CLKLAT/DAC Rev. B | Page 29 of 36 VDL GND 4Y U5 R20 1k VDL E52 E53 5 9 10 12 13 R37 25 Rx DNP DR 3A 3B 4A 4B R22 0 ENCODE GND E31 R21 1k VDL E43 E44 GND E35 C43 0.1F R31 1k VDL J2 R30 1k R29 50 GND GND GND R24 1k VDL GND 03066-A-052 AD9236 AD9236 03066-0-055 03066-0-053 Figure 51. LFCSP Evaluation Board Layout, Primary Side Figure 53. LFCSP Evaluation Board Layout, Ground Plane 03066-0-054 03066-0-056 Figure 52. LFCSP Evaluation Board Layout, Secondary Side Figure 54. LFCSP Evaluation Board Layout, Power Plane Rev. B | Page 30 of 36 AD9236 03066-0-057 03066-0-058 Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. B | Page 31 of 36 AD9236 Table 12. LFCSP Evaluation Board Bill of Materials Item Qty. Omit 1 Reference Designator 1 18 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C18, C27, C17, C28, C35, C45, C44 2 8 C2, C3, C4, C10, C20, C22, C25, C29 2 C46, C24 3 4 5 6 8 1 1 2 9 2 7 8 9 10 11 12 13 2 1 1 1 5 6 2 14 C14, C30, C32, C38, C39, C40, C48, C49 C19 C26 C21, C23 E31, E35, E43, E44, E50, E51, E52, E53 E1, E45 J1, J2 L1 P2 P12 R3, R12, R23, R28, RX R37, R22, R42, R16, R17, R27 R4, R15 R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, R36 R10, R11 R29 1 16 17 18 19 20 21 22 23 24 25 26 27 Total 81 1 Device Chip Capacitors Package 0603 Value 0.1 F Recommended Vendor/Part No. Supplied by ADI Tantalum Capacitors TAJC 10 F Chip Capacitors Chip Capacitor Chip Capacitors Headers 0603 0603 0603 EHOLE 0.001 F 20 pF 10 pF Jumper Blocks SMA Connectors/50 Inductor Terminal Block Header Dual 20-Pin RT Angle Chip Resistors Chip Resistors Chip Resistors SMA 0603 TB6 HEADER40 0603 0603 0603 0 33 1 k 10 nH Coilcraft/0603CS10NXGBU Wieland/25.602.2653.0, z5-530-0625-0 Digi-Key S2131-20-ND 14 15 2 1 2 1 1 1 1 1 1 1 5 4 2 1 35 Chip Resistors Chip Resistor Resistor Pack ADT1-1WT AD9236BCP ADC (DUT) 74VCX86M AD92XXBCP/PCB AD8351 Op Amp M/A-COM Transformer Chip Resistors Chip Resistors Chip Resistors Chip Resistor 0603 0603 R_742 AWT1-1T CSP-32 SOIC-14 PCB MSOP-8 36 50 220 Digi-Key CTS/742C163221JTR Mini-Circuits Analog Devices, Inc. Fairchild Analog Devices, Inc. Analog Devices, Inc. M/A-COM/ETC1-1-13 SELECT 25 10 k 1.2 k X X X R19 RP1, RP2 T1 U1 U4 U5 PCB U3 T2 R9, R1, R2, R38, R39 R18, R14, R33, R35 R40, R41 R34 74LVTH162374 CMOS Register TSSOP-48 ETC1-1-13 1-1 TX 0603 0603 0603 These items are included in the PCB design, but are omitted at assembly. Rev. B | Page 32 of 36 AD9236 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45 SEATING PLANE 0.20 0.09 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 57. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 17 16 8 3.25 3.10 SQ 2.95 0.50 0.40 0.30 9 0.25 MIN 3.50 REF 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters Rev. B | Page 33 of 36 AD9236 ORDERING GUIDE Model AD9236BRU-80 AD9236BRURL7-80 AD9236BRUZ-80 1 AD9236BRUZRL7-801 AD9236BCP-80 2 AD9236BCPRL7-802 AD9236BCPZ-801, 2 AD9236BCPZRL7-801, 2 AD9236BRU-80EB AD9236BCP-80EB2 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 32-Lead Lead Frame Chip Scale (LFCSP_VQ) 32-Lead Lead Frame Chip Scale (LFCSP_VQ) 32-Lead Lead Frame Chip Scale (LFCSP_VQ) 32-Lead Lead Frame Chip Scale (LFCSP_VQ) TSSOP Evaluation Board LFCSP Evaluation Board Package Option RU-28 RU-28 RU-28 RU-28 CP-32-2 CP-32-2 CP-32-2 CP-32-2 Z = Pb-free part. It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. Rev. B | Page 34 of 36 AD9236 NOTES Rev. B | Page 35 of 36 AD9236 NOTES (c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03066-0-1/06(B) Rev. B | Page 36 of 36 |
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